1. Field of the Invention
This invention relates to a digital video signal coding circuit for coding a digital video signal with data compression, a decoding circuit for decoding a digital video signal coded by the digital video signal coding circuit, and a helical scan video tape recorder including these circuits.
2. Description of the Prior Art
A digital coding circuit for coding a digital video signal with data compression used in a digital VTR is known. This digital coding circuit codes the digital video signal through a quadrature conversion orthogonal transforming means circuit, a variable length coding circuit, an error correction coding circuit, and a record coding circuit in order to record the digital video signal on a recording medium, such as a magnetic tape. A digital decoding circuit decoding a reproduced digital video signal reproduced from the recording medium, on which the digital video signal has been recorded as mentioned above, through a data detection circuit, an error correction circuit, a variable length decoding circuit, and a quadrature inverse conversion circuit.
Generally, in the case of non-industrial use digital VTRs or home use digital VTRs, because the number of manufactured apparatus is larger than that of the industrial use digital VTRs, the development and manufacturing costs of ICs used in the non-industrial use digital VTR is low. Contrary, because the number of manufactured high picture quality digital VTRs is extremely small generally, the development and manufacturing costs of ICs per set tends to be high.
Therefore, there is such an idea that a cost of a high picture quality digital VTR can be reduced by using common signal processing ICs between non-industrial use digital VTRs and high picture quality digital VTRs.
In the non-industrial use digital VTR or home use digital VTR, a cassette size (tape length) should be determined in consideration of not only picture quality but a recording duration and ease in handling of the cassette. Generally, there is a tendency that a small cassette size is preferred, which is provided by making a coding compression rate large to the extent of 1/4 to 1/tens. On the other hand, in the high picture quality digital VTR, because the picture quality is important, a relatively small coding compression rate such as 1/2 to 1/4 is selected.
Here, "small coding compression" means that an amount of data recorded/reproduced on/from a video tape is large. In other words, an amount of data per unit interval which a signal processing circuit of a high picture quality digital VTR should process is large. Accordingly, the signal processing circuit is required to operate at a high speed.
However, generally, the demand for the high speed operation makes a circuit scale large. On the other hand, from a point of view of the manufacturing cost and the reduction of power consumption, the circuit scale of the signal processing circuit in the IC should be made as small as possible.
From the point of view as mentioned above, it is extremely desirable that internal circuits in a signal processing IC for the non-industrial used digital VTR are unchanged and a signal processing circuit for a high quality digital VTR is formed by using a plurality of such ICs or by using such an IC with some external additional circuits. This idea is also applicable to the digital disc recorder or the like.
FIG. 10 is a block diagram of an example of such a prior art digital coding circuit and decoding circuit used in a prior art digital VTR. FIG. 11 is a partial block diagram of the prior art digital coding circuit shown in FIG. 10. In FIGS. 10 and 11, an analog video signal is inputted to an A/D converter 10 for converting the analog video signal into a digital video signal. Then, the digital video signal is supplied a frame memory 11 for temporary store the digital video signal for DCT (Discrete Cosine Transform) conversion. Then, the digital video signal is supplied to a DCT circuit 50 of a quadrature conversion circuit 12 for effecting a DCT processing, i.e., the DCT conversion, to provide coefficient data. The coefficient data are supplied to a zigzag scanning circuit 52. FIG. 12 is an illustration for showing a prior art zigzag scanning. The zigzag scanning circuit 52 scans the coefficient data and outputs of the coefficient data serially in the order as shown in FIG. 12. The coefficient data after zigzag scanning are supplied to a separating circuit 14 for separating the coefficient data into odd number.sup.th data and even number.sup.th data trains wherein ordinal numbers are shown in FIG. 12. FIG. 14 is a block diagram of an example of the separating circuit 14. In FIG. 14, the first data D(0) of the DCT coefficient data zigzag-scanned is written into either of FIFO memories 14A and 14B, for example, the FIFO memory 14A. The next second data D(1) is written into the FIFO memory 14B. Similarly, the following data D(2), D(3), D(4), . . . are written in to FIFO memories 14A and 14B alternately. That is, even number.sup.th data is stored in the FIFO memory 14A as an even number.sup.th data train and odd number.sup.th data is stored in the FIFO memories 14B as an odd number.sup.th data train.
Then, each data train separated by the FIFO memories 14A and 14B is supplied to each of data addition switches 14D and 14E. In these switches, data "0" is added to thirty-third to sixty-fourth data of each data train including thirty-two data. Therefore, if the above-mentioned processing is effected to the first to sixty-fourth data which are assumed to be other than "zero", data other than "0" exist at only from first to thirty-second data and two sets of data trains, each having possibility of the number of data other than "0" is a half of the number before the processing, are obtained. A control circuit 14C effects the writing and the reading of data in each of memories 14A and 14B and the switching control of switches 14D and 14E. The control circuit 14C may be formed commonly to the system controller 66 (refer to FIG. 11).
The even and odd number.sup.th coefficient data trains produced as mentioned are supplied to variable length coding circuits 16A and 16B respectively as shown in FIGS. 10 and 11. Then, quantizers 60A and 60B effect the quantization processing for approximating the coefficient data trains with discrete levels respectively. Coarseness of the quantizing levels is-controlled by the coding amount control circuits 62A and 62B, that is, these circuits provide so-called non-linear quantization.
Then, the quantized coefficient data trains are supplied to the two-dimensional Huffman coding circuits 64A and 64B respectively. Then, the variable length coding processings are effected wherein a short code is assigned to a level where a degree of occurrence frequency is high. Concretely, the two-dimensional Huffman coding for two-dimensionally assigning of codes through combining a zero-run-length and a value of coefficient data after the quantizing is effected. A system controller 66 controls respective circuits.
Then, output signals of the two-dimensional Huffman coding circuits 64A and 64B are further subjected to coding for error correction by the error correction coding circuits 18A and 18B and coding for recording by record coding circuits 20A and 20B. Then, data after final coding are recorded by recording heads 24A and 24B on a video tape 26 after amplification by amplifiers 22A and 22B.
Then, the reproducing side will be described. Data reproduced by reproducing heads 28A and 28B from the video tape 26 is amplified by amplifiers 30A and 30B and then, supplied to data detection circuits 32A and 32B for detecting video data other than synchronizing signals and control signals. Then, error detection and correction by error correction circuits 34A and 34B detect errors and correct the errors and then, variable length decoding circuits 36A and 36B decode the corrected data. The decoded data are mixed by a mixing circuit 38, that is, a reverse processing to the separation circuit 14 is effected.
Data trains after mixing are decoded by a quadrature inverse conversion circuit 40, i.e., a quadrature inverse conversion which is reverse to the DCT conversion is effected. Further, the output of the frame memory 41 is converted into an analog video signal by a D/A converter 42. As mentioned, the decoding of data from the reproduced video data is effected.
As mentioned, the coefficient data after the quadrature conversion are subjected to processings such as coding with the coefficient data separated into two, each of two being subjected to further processings. Therefore, a high picture quality digital VTR is provided, which is capable of processing the digital video signal at about twice as much amount of information as the conventional structure though signal processing ICs for the non-industrial use VTR are used.
Here, the number of order of the two-divisional DCT effected in the quadrature conversion circuit 12 is generally 8.times.8 pixels. This is mainly used in the case of the processing of video data within a frame. If an ordinary clock frequency for the video processing is used, it is convenient to deal 8.times.8 pixels as a unit because the quadrature conversion is effected at an approximately square region within the frame.
However, there are cases that the number of order of DCT should be changed. FIG. 13 shows illustrations of prior art for showing partial images on a screen or extracted images. For example, it is assumed that there is a vertical bar ST on a reproduced image as shown by a frame image 13a and a camera taking this image is panned in a lateral direction (in a direction denoted by an arrow FA). In this case, a portion (8.times.8 pixels) is extracted from the frame image 13a and the result is shown by the illustration 13b for example. This is separated into respectively images of even and odd fields as shown by illustrations 13c and 13d.
In such a situation, it is known that the conversion coefficients concentrate to a lower frequency component when images of the odd and even fields are separated and the two-dimensional DCT is effected with respect to 8.times.4 pixels than the case would be obtained by the two dimensional DCT effected with the 8.times.8 pixels as a unit within a frame as shown by the illustration 13b. Then, in the case of such image, two-dimensional DCTs of 8.times.8 and 8.times.4 are switched adaptively. If such switching processing is effected, an amount of lost of information decreases, so that a high picture quality is provided.
However, if such a switching of the number of order is applied to the prior art mentioned above merely, there is a case where information of the first and second fields is mixed in the data train after separation of data after zigzag scanning. This is not good for the searching because heads traverse tracks slantwise, so that a reproduced signal is obtained partially from the relation of azimuth. Thus, there is a case where only either of two data trains after separation is obtained.
In such a case, if an image is reproduced from only either data train, the block distortion is prominent in the reproduce image because the DCT inverse conversion is effected with a half of data. Here, if data of the other field is mixed with in the data train after separation, the number of data used for the DCT inverse conversion is less than a half, so that the picture quality further decreases. A helical scan digital video tape recorder including these coding and decoding circuits. In such a helical scan digital video tape recorder, there is problem in that in the searching mode, the picture quality reproduced in the searching mode is not sufficient.